1. Field of the Invention
Certain embodiments of the present invention relate, in general, to an improved semiconductor manufacturing process, and in particular, to an-overlay mark design to reduce the overlay shift during the semiconductor manufacturing process.
2. Description of the Related Art
Integrated circuits (ICs) are formed by providing one or more layers sequentially on a semiconductor substrate. These layers can include a polysilicon layer, dielectric layers such as oxide or nitride layers, and metal layers such as silicide, tungsten, and copper layers. The layers can be patterned or etched to form IC parts or features. In recent years, the sizes of integrated circuit devices have continued to decrease thereby increasing the packing densities of these devices considerably. As the result, the performance of the integrated circuit devices has been improved while reducing the manufacturing cost.
However, smaller process parameters cause problems relating to the performance of these integrated circuit devices. For example, one of the most critical process control techniques used in the manufacturing of ICs is the measurement of overlay accuracy between the successive, patterned layers on a semiconductor substrate. Generally, overlay marks are used to make sure that the successive, patterned layers are deposited in proper positions. One of the most commonly used overlay patterns is having a box within a bigger box in the scribe line areas outside the IC core or device area. FIG. 1 illustrates a typical “box” type overlay mark. The inner box is typically printed on the top layer of the semiconductor substrate being produced, while the open-centered outer box is printed on the second top layer of the semiconductor substrate. The measurement process thus involves imaging of the target on an electronic camera or a microscope system, at high magnification and with high resolution in both x and y directions.
Shown in FIGS. 2A and 2B are a top view and a cross-sectional view of a portion of an integrated circuit memory device according to a conventional overlay mark structure. In this conventional structure, four distinctive overlay marks or so-called “box to box overlay marks” are employed to form two chopped boxes in an inner bar 205 and an outer bar 201 for alignment purpose. FIG. 2B shows a cross-sectional view of a portion of an integrated circuit memory device after the metal patterning photoresist developing has been performed. It includes an interlayer dielectric (ILD) layer 212 on a semiconductor substrate 210, a plurality of contact openings (not shown in the figure), a metal layer 214 such as an AlCu layer and a metal cap layer such as a Ti/TiN composite layer 216 over the openings and the entire surface, and a photoresist mask 218 formed over the metal layer 214. Ideally, the remaining metal mark after the metal etch step should have no wafer induced overlay shift between the contact opening and the metal line. In reality, however, a wafer induced overlay shift exists between the contact opening and the metal line because of the overlay mark profile becoming asymmetric after the metal line film deposition step. The wafer edge has a larger overlay shift compared to the wafer center after the metal film deposition step. Such an overlay shift is called “scalling effect.” There are two causes to induce such phenomena. One is a self-shadowing effect on the mark depth and the deposition angle as illustrated in FIG. 6. The other is caused by the metal stress 214 on the wafer surface. Moreover, a severe metal line scaling effect can result as the metal line thickness is increased due to the higher metal stress.
Referring now to FIG. 3A, a portion of a partially completed semiconductor device is shown. The figure shows a portion of a device region 310 on the right hand side and also a portion of a scribe region 330 on which the overlay marks will be built on the left hand side.
First, the transistor structure including a gate, a drain, and source regions (not shown in the figures) are formed on a semiconductor substrate 300. Thereafter, the structures are patterned by the conventional photolithography and etching techniques. Next, an interlayer dielectric (ILD) layer 302 is first formed over the entire semiconductor substrate. Thereafter, contact openings 305 are formed. A first metal layer structure 304 is then deposited and etched backed to form a metal plug in the device area, and the metal residues are left in the sidewalls of the overlay mark in the scribe line area as shown in FIG. 3A. Then, a second metal layer structure 308 is deposited to form the first metal interconnect layer over the entire semiconductor substrate 300 as shown in FIG. 3A.
In one example, the first metal layer 304 is a tungsten layer formed by the conventional chemical vapor deposition (CVD) technology. As shown in FIG. 3B, going from the bottom to the top on the ILD layer 302, the multilayer metal film scheme 308 may include a TiN underlayer 308a, and an A1 metal layer 308b, and Ti 308c and TiN 308d top layers. In another example, the thickness of each layer is in the range of 300 to 600 angstroms for a TiN underlayer 308a, in the range of 2000 to 10000 angstroms for an A1 metal layer 308b, in the range of 100 to 300 angstroms for a Ti 308c layer, and in the range of 200 to 600 angstroms for a TiN 308d to layer.
Referring now more particularly to FIG. 3C, a portion of a partially completed semiconductor device after the photoresist coating and exposure steps is shown. The figure also shows a portion of a device region 310 on the right hand side and also a portion of a scribe line region 330 on which the overlay marks will be built on the left hand side. Since the top metal layer has higher stress compared with the underlying ILD layer, the edge of the metal profile 309 becomes asymmery after the metal deposition process steps. It causes the remaining photoresist patterns 312 to shift from the ideal symmatry profile slightly toward the left. When performing the overlay shift measurement, the actual overlay will be A1 and B1 compared with the ideal situation of A and B. Therefore, after the metal etch step, so called “scalling effect” occurs, resulting in the metal patterns 308a not completely covering the contact hole in the device area 305b as shown in FIG. 3D. This type of misalignment will severely effect the electrical performance and reliability of the integrated circuits.
Therefore, there is a need for a new and improved overlay mark design which can effectively solve the above-mentioned problems in the prior art method.